Motivation / Story
The control law is not the final actuator command控制律本身并不是最终执行命令
Up to the current loop, many derivations behave as if the motor can receive any commanded voltage immediately. Chapter 5 corrects that fiction. The inverter is not an ideal copier of $u_d^*$ and $u_q^*$; it is a switching device with a finite dc bus, finite duty ratio, and discrete switching states.
在讲到电流环之前，很多推导默认电机可以立刻获得任意期望电压。第五章就是来修正这个假设的。逆变器不是 $u_d^*$、$u_q^*$ 的理想复制器，而是一个受母线电压、占空比和离散开关状态约束的器件。
Class message课堂主旨
Once the controller output approaches the voltage limit, bandwidth, tracking quality, anti-windup behavior, and high-speed performance all become inverter questions.
一旦控制器输出逼近电压上限，带宽、跟踪质量、抗积分饱和和高速性能就都变成了逆变器问题。
Before this chapter本章之前
- Voltage references are derived in $dq$ or $\alpha\beta$ coordinates.电压参考在 $dq$ 或 $\alpha\beta$ 坐标系中推导。
- The controller output looks continuous and unconstrained.控制器输出看起来是连续且不受限的。
- The plant input is often idealized.执行端通常被理想化。
After this chapter本章之后
- A finite dc bus determines the reachable voltage set.有限的母线电压决定了可达电压集合。
- PWM maps a reference into switching times and duty ratios.PWM 把参考量映射成开关时间和占空比。
- Modulation strategy directly affects usable bandwidth.调制策略直接影响可用带宽。
5.1 / Saturation and Bandwidth
The inverter should be viewed as a constrained actuator把逆变器看成受限执行器
The current loop is not limited only by controller gains. It is also limited by how fast the inverter can change the applied voltage. If the motor back-EMF grows with speed, a large part of the dc bus is already consumed just to cancel that EMF, leaving less remaining voltage for current regulation.
电流环的极限不只由控制器参数决定，还取决于逆变器能多快改变施加到电机上的电压。随着转速升高，反电动势变大，母线电压中越来越大的一部分要先用来抵消反电动势，留给电流调节的余量就更少了。
A practical interpretation is一个很实用的理解是
$$\text{available control voltage} = V_{dc}\text{-limited capability} - \text{back-EMF requirement}.$$
Bandwidth带宽
Higher bandwidth demands faster voltage change. That demand is meaningless if the inverter has no voltage headroom left.更高带宽意味着更快的电压变化。如果逆变器已经没有电压余量，这个要求就无从实现。
Saturation饱和
When the command exceeds the realizable range, integrators can wind up and the loop can lose the behavior predicted by linear design.当指令超出可实现范围时，积分器会累积误差，闭环行为也会偏离线性设计时的预期。
High-speed region高速区
At high speed, voltage rather than current often becomes the first hard constraint.在高速区，首先触碰到的硬约束往往不是电流，而是电压。
5.2 / Topology
Three-phase three-wire inverter: what is really controlled?三相三线逆变器：真正被控制的是什么？
The controller eventually chooses switching variables such as $S_a, S_b, S_c$. Those switching states determine terminal potentials and thus line voltages. The key physical point is that in a three-wire system, line voltages matter more directly than phase-to-neutral voltages.
控制器最终要决定的是类似 $S_a, S_b, S_c$ 这样的开关变量。它们决定各相端点电位，从而决定线电压。三相三线系统中最关键的物理事实是：真正更直接受约束、也更有意义的是线电压，而不是某个假想中性点的相电压。
Switching states开关状态
The inverter can only connect a phase terminal to the positive or negative dc rail.逆变器每一相最终只能被接到正母线或负母线。
Line voltage线电压
Differences such as $u_{ab}=u_a-u_b$ are what directly drive the machine windings.像 $u_{ab}=u_a-u_b$ 这样的差值才是直接驱动电机绕组的量。
Common mode共模量
Adding the same offset to all three phase commands changes terminal potentials but leaves every line voltage unchanged.给三相参考同时加上同一个偏置，会改变端点电位，但不会改变任何线电压。
If we add a zero-sequence term $u_0$ to all three phase commands, then如果给三相相电压参考都加上零序项 $u_0$，则
$$
(u_a+u_0)-(u_b+u_0)=u_a-u_b,
\qquad
(u_b+u_0)-(u_c+u_0)=u_b-u_c.
$$
So line voltages are unchanged.因此线电压完全不变。
5.3.1–5.3.2 / Baseline
SPWM is intuitive, but it does not use the dc bus fullySPWM 很直观，但它没有把母线用满
Sine-triangle PWM is the natural first idea: build three sinusoidal phase references and compare them with a carrier. The method is clean and easy to implement. But it leaves the common-mode degree of freedom unused, so the three-phase span is not packed tightly against the dc bus limits.
正弦三角波 PWM 是最自然的起点：构造三相正弦参考，再和载波比较。这个方法很干净，也很容易实现。但它没有使用零序自由度，因此三相参考的整体跨度并没有被紧密地贴到母线极限上。
Physical conclusion物理结论
Under standard SPWM, the maximum phase-voltage amplitude is limited to $V_{dc}/2$.在标准 SPWM 下，相电压参考的最大幅值被限制在 $V_{dc}/2$。
The maximum line-voltage amplitude becomes only $0.866V_{dc}$.因此最大线电压幅值只有 $0.866V_{dc}$。
Interpretation解释
The problem is not that SPWM is wrong. The problem is that it uses only one particular placement of the three phase references, even though many placements produce the same line voltages.问题并不是 SPWM 错了，而是它只使用了三相参考的一种摆放方式。事实上，许多不同的摆放方式都能得到同样的线电压。
Useful classroom sentence适合课堂强调的一句话
SPWM does not fail because of the sinusoid. It under-utilizes the bus because it ignores the freedom to shift all three phase commands together.
SPWM 的不足不在于“正弦”本身，而在于它忽略了三相参考可以整体平移的自由度。
5.3.3–5.3.4 / Core Idea
SVPWM: use zero-sequence injection to reposition the phase commandsSVPWM：利用零序注入重新摆放三相相电压参考
The core move of SVPWM is concrete: add a carefully chosen common-mode term so that the midpoint of the phase-command span is moved toward the center of the dc bus. The line voltages stay the same, but the available voltage range is used much more effectively.
SVPWM 的核心动作非常具体：加入一个精心选择的共模项，让三相相电压参考的整体中点尽量对准母线中点。线电压目标保持不变，但可用电压范围被更有效地利用起来了。
A convenient zero-sequence choice is一种很常见的零序选择是
$$
u_0=-\frac{\max(u_a^*,u_b^*,u_c^*)+\min(u_a^*,u_b^*,u_c^*)}{2}.
$$
This centers the span of the three phase commands and leads to the usual SVPWM / midpoint-clamped zero-sequence modulation law.它会把三相相电压参考的整体跨度重新居中，这就导向了常见的 SVPWM / 中点钳位零序调制规律。
What stays unchanged?什么不变？
The desired line-voltage waveforms stay unchanged.目标线电压波形不变。
What changes?什么改变？
The phase-command placement relative to the dc rails changes.三相参考相对于母线轨的摆放位置改变了。
Why is this useful?为什么有用？
It increases usable voltage amplitude before saturation.它提高了进入饱和之前可用的电压幅值。
The standard utilization improvement is标准结论是
$$
\frac{V_{SVPWM}}{V_{SPWM}} = \frac{2}{\sqrt{3}} \approx 1.1547.
$$
That is, SVPWM gives about 15.47% more usable voltage amplitude than SPWM.也就是说，相比 SPWM，SVPWM 大约多提供 15.47% 的可用电压幅值。
Most important takeaway最重要的结论
SVPWM is not mainly about memorizing a hexagon. It is about exploiting the zero-sequence degree of freedom so that the three-phase span sits as close as possible to the dc-bus limits.
SVPWM 最重要的不是记住一个六边形，而是理解：它利用零序自由度，让三相参考尽量贴近母线极限。
Appendix G / Bridge to Implementation
From equations to the repository code从理论公式走到仓库代码
The practical bridge for this class is already in the repository: simulation/tutorials_ep6_svpwm.py. The code contains an SVPWM object, a function called SVGEN_DQ, duty-ratio variables T_a,T_b,T_c, and a simulation switch that can turn detailed inverter behavior on or off.
这节课的工程落点已经在仓库里：simulation/tutorials_ep6_svpwm.py。代码里已经有 SVPWM 对象、SVGEN_DQ 函数、占空比变量 T_a,T_b,T_c，以及一个能开关详细逆变器仿真的参数。
| Theory block理论模块 |
Code handle代码对应 |
What to look for要观察什么 |
| Inverse Park output逆 Park 输出 |
CTRL.cmd_uab[0], CTRL.cmd_uab[1] |
This is the voltage reference in the $\alpha\beta$ frame.这就是 $\alpha\beta$ 坐标系下的电压参考。 |
| SVPWM coreSVPWM 核心 |
SVGEN_DQ(v, one_over_Vdc) |
Normalization, sector logic, and the construction of T_a,T_b,T_c.归一化、扇区判断，以及 T_a,T_b,T_c 的构造。 |
| Duty limits占空比限制 |
SYSTEM_MAX_PWM_DUTY_LIMATATION, SYSTEM_MIN_PWM_DUTY_LIMATATION |
Why the implementation avoids exactly 0 and 1 duty.为什么实现中故意避免 0 和 1 的极限占空比。 |
| Detailed inverter model详细逆变器模型 |
MACHINE_SIMULATIONs_PER_SAMPLING_PERIOD |
Set to 1 for fast idealized behavior; set to a larger value to enable switching-level SVPWM effects.设为 1 时是快速近似；设大一些时会启用更真实的开关级 SVPWM 效果。 |
| Voltage headroom assumption电压余量假设 |
DC_BUS_VOLTAGE / 1.732 |
The current-loop limit already assumes an SVPWM-style usable phase-voltage bound.电流环的限幅里已经写入了基于 SVPWM 的相电压可用上限假设。 |
Follow the signal path: $u_{dq}^* \rightarrow u_{\alpha\beta}^* \rightarrow SVGEN_DQ \rightarrow T_a,T_b,T_c$.沿着信号链去看：$u_{dq}^* \rightarrow u_{\alpha\beta}^* \rightarrow SVGEN_DQ \rightarrow T_a,T_b,T_c$。
Ask where the dc-bus limit enters the computation.追问母线电压限制是从哪一步进入计算的。
Ask where the implementation reveals the difference between ideal voltage commands and realizable inverter output.追问代码里哪一部分体现了“理想电压命令”和“真正可实现输出”的差别。
Discussion / Think in Class
Questions students should be able to answer after this lecture学完本讲后学生应能回答的问题
Q1
Why is the inverter best understood as a constrained actuator rather than as a transparent amplifier?为什么把逆变器理解成“受限执行器”比理解成“透明放大器”更准确？
Q2
Why does high speed make voltage saturation more likely, even when current limits are unchanged?为什么即使电流限制不变，转速升高后也更容易碰到电压饱和？
Q3
Why can adding the same zero-sequence term to all three phase commands leave every line voltage unchanged?为什么给三相参考都加同一个零序项，不会改变任何线电压？
Q4
What exactly is under-utilized in SPWM, and what freedom does SVPWM exploit?SPWM 到底浪费了什么？SVPWM 又利用了什么自由度？
Q5
Why is the ratio $2/\sqrt{3}$ not just a number to memorize, but a statement about usable voltage headroom?为什么 $2/\sqrt{3}$ 不只是一个结论数字，而是在说明可用电压余量的变化？
Q6
Why does the code already need to know the assumed modulation method when it sets the current-loop voltage limit?为什么代码在设置电流环输出限幅时，就已经必须知道调制方式的假设？