Lecture 6 - Inverter Modeling

Motivation / The Missing Block

The controller commands voltage, but the inverter delivers events控制器给的是电压指令，逆变器交付的是开关事件

A field-oriented controller usually outputs $u_d^*$ and $u_q^*$. After inverse Park and SVPWM, this becomes three duty ratios. But the motor terminals do not see duty ratios directly. They see phase-leg switching states, dc-bus rails, diode conduction during dead time, and a waveform whose average may or may not match the command over one PWM period. FOC 控制器通常输出 $u_d^*$ 和 $u_q^*$。经过逆 Park 和 SVPWM 之后，它们变成三相占空比。但电机端子并不会直接“看见占空比”。它看见的是桥臂开关状态、直流母线电平、死区期间的二极管续流，以及一个在一个 PWM 周期内平均值可能等于也可能偏离指令的波形。

One sentence model hierarchy一句话模型层级 An average inverter model answers low-frequency control questions; a switching model answers ripple, sampling, common-mode, and implementation questions; a nonideal model answers why experiments refuse to look ideal. 平均逆变器模型回答低频控制问题；开关模型回答纹波、采样、共模和实现问题；非理想模型回答为什么实验结果不愿意长得那么理想。

Modeling / Choose the Right Resolution

Three useful inverter models三种常用逆变器模型

Model模型	Motor input给电机的输入	Good for适合分析	Can hide会隐藏什么
Ideal voltage source理想电压源	`u_alpha_beta = command`	Control design, observer tuning, fast sweeps.控制器设计、观测器调参、快速扫参。	PWM delay, ripple, bus saturation, common mode.PWM 延迟、纹波、母线饱和、共模电压。
Average inverter平均逆变器	`u_xG = d_x V_dc`	Voltage limitation, modulation comparison, low-frequency phase error.电压限幅、调制方式比较、低频相位误差。	Carrier-frequency ripple and exact switching sequence.载波频率纹波和精确开关序列。
Switching inverter开关逆变器	`u_xG = S_x V_dc`	Ripple, sampling instant, common-mode voltage, discrete implementation.纹波、采样点、共模电压、离散实现。	Semiconductor loss unless device model is added.若不加器件模型，仍然看不到损耗细节。
Nonideal switching非理想开关模型	`S_x` + dead time + drops	Current distortion, low-speed error, compensation design.电流畸变、低速误差、补偿设计。	Thermal and EMI details unless more physics is included.若不继续加物理细节，仍看不到热和 EMI 全貌。

Equations / Switching Model

From phase-leg states to motor phase voltages从桥臂状态到电机相电压

For a two-level inverter, let $S_a,S_b,S_c\in\{0,1\}$ denote whether the upper switch of each phase leg is on. The terminal-to-negative-bus potentials are: 对于两电平逆变器，令 $S_a,S_b,S_c\in\{0,1\}$ 表示各相上管是否导通。各相端子相对于母线负端的电位为：

$$u_{aG}=S_a V_{dc},\qquad u_{bG}=S_b V_{dc},\qquad u_{cG}=S_c V_{dc}$$

In a three-phase three-wire motor, the neutral potential is not fixed by an external wire. For a balanced star-connected machine model, the neutral-to-bus potential is the average terminal potential: 三相三线制电机没有外部中性线，中性点电位不是被外部强行固定的。对于对称 Y 接电机模型，中性点相对母线负端电位就是三相端电位的平均：

$$u_{nG}=\frac{u_{aG}+u_{bG}+u_{cG}}{3}$$

The actual winding voltages are therefore terminal potentials minus neutral potential: 因此真正加在绕组上的相电压是端电位减去中性点电位：

$$u_{an}=u_{aG}-u_{nG},\qquad u_{bn}=u_{bG}-u_{nG},\qquad u_{cn}=u_{cG}-u_{nG}$$

Common trap常见坑 $u_{aG}$ is not the same thing as $u_{an}$. The first is a terminal potential relative to the dc bus. The second is the winding voltage that enters the machine equation. $u_{aG}$ 不等于 $u_{an}$。前者是端子相对直流母线负端的电位，后者才是进入电机方程的绕组电压。

Equations / Average Model

The average model keeps the useful voltage and removes the carrier平均模型保留有用电压，去掉载波细节

If the machine electrical dynamics are much slower than the PWM period, one period can be replaced by its average. With duty ratios $d_a,d_b,d_c$, the terminal potentials become: 如果电机电气动态明显慢于 PWM 周期，可以用一个周期内的平均值代替开关波形。对于占空比 $d_a,d_b,d_c$，端电位为：

$$\bar u_{aG}=d_a V_{dc},\qquad \bar u_{bG}=d_b V_{dc},\qquad \bar u_{cG}=d_c V_{dc}$$

The same neutral subtraction gives the average winding voltages: 同样减去中性点平均电位，就得到平均绕组电压：

$$\bar u_{an}=V_{dc}\left(d_a-\frac{d_a+d_b+d_c}{3}\right)$$

This is why adding the same offset to all three duty ratios changes common-mode voltage but not line-to-line voltage or balanced winding voltage. That little degree of freedom is the quiet machinery behind SVPWM. 这也解释了为什么给三相占空比同时加同一个偏置，会改变共模电压，却不会改变线电压或对称绕组电压。SVPWM 背后那个小小的自由度就在这里。

Discrete-Time / Timing Matters

PWM update delay is an inverter model tooPWM 更新延迟也是逆变器模型的一部分

In real code, the controller samples currents, computes voltage commands, writes compare registers, and the PWM hardware applies those compare values at a synchronization event. This creates an effective delay between the measured current and the realized voltage. 真实代码里，控制器先采样电流，再计算电压指令，再写入比较寄存器，最后 PWM 硬件在同步事件处应用这些比较值。这会在“测到的电流”和“实际输出的电压”之间产生有效延迟。

Why it matters in $dq$为什么在 $dq$ 里重要

A pure time delay looks like phase lag. In a rotating frame, phase lag couples $d$ and $q$ behavior and can reduce current-loop bandwidth.纯时间延迟表现为相位滞后。在旋转坐标系中，相位滞后会耦合 $d$、$q$ 行为，并降低电流环可用带宽。

Simple approximation简单近似

For control analysis, the inverter and computation delay is often modeled as $e^{-sT_d}$ or a first-order lag with similar low-frequency phase.做控制分析时，逆变器与计算延迟常被近似成 $e^{-sT_d}$，或者近似成低频相位相近的一阶滞后。

$$G_{\mathrm{inv}}(s)\approx e^{-sT_d}\qquad\text{or}\qquad G_{\mathrm{inv}}(s)\approx \frac{1}{1+sT_d}$$

Nonideal / Dead Time and Drops

Dead time creates a voltage error that depends on current direction死区会制造一个依赖电流方向的电压误差

Dead time prevents shoot-through by briefly turning both devices in a phase leg off during commutation. During that interval, the phase current chooses the diode or device path, so the terminal voltage depends on current sign. A useful first-order model is: 死区通过在换相时让同一桥臂上下管短暂同时关断来防止直通。在这段时间内，相电流会选择二极管或器件续流路径，因此端电压与电流方向有关。一个常用的一阶模型是：

$$\Delta u_x \approx -\operatorname{sgn}(i_x)\frac{t_{dead}}{T_{pwm}}V_{dc},\qquad x\in\{a,b,c\}$$

This approximation is intentionally simple. It captures the most important lesson for control: the inverter error is not just noise. It is a structured disturbance correlated with phase current. 这个近似刻意保持简单。它抓住了控制上最重要的一点：逆变器误差不只是噪声，而是一个与相电流方向相关的结构化扰动。

Low-speed warning低速提醒 At high speed, back EMF may dominate small inverter errors. At low speed, dead-time voltage error can become a surprisingly visible part of the voltage budget. 高速时反电势可能盖过小的逆变器误差；低速时，死区电压误差可能在电压预算里变得非常显眼。

Repository / Bridge to Simulation

Where this lands in ACMSimPy这些内容在 ACMSimPy 里落在哪里

The practical bridge is still the SVPWM tutorial path. The important shift for this lecture is to separate the modulation calculation from the inverter model that feeds the machine ODE. 工程落点仍然是 SVPWM tutorial 这条线。本讲的关键转变是：把“调制计算”与“真正喂给电机 ODE 的逆变器模型”分开看。

Concept概念	Code handle代码抓手	Question to ask要问的问题
Duty generation占空比生成	`SVGEN_DQ`, `T_a,T_b,T_c`	What duty ratios did the controller request?控制器请求了什么占空比？
Switching realization开关实现	`gate_signal_generator`, `S1`...`S6`	What switching states did the motor actually see?电机实际看到了哪些开关状态？
Terminal potential端电位	`voltage_potential_at_terminal`	Is this bus-referenced potential or winding voltage?这是母线参考端电位，还是绕组电压？
Model resolution模型分辨率	`MACHINE_SIMULATIONs_PER_SAMPLING_PERIOD`	Are we averaging the inverter or resolving switching events?我们是在平均逆变器，还是在解析开关事件？

Discussion / Think in Class

Questions students should be able to answer学完本讲后学生应能回答的问题

Q1

When is an ideal voltage-source inverter model good enough?什么时候理想电压源逆变器模型已经够用？

Q2

Why must $u_{xG}$ and $u_{xn}$ be kept separate in a three-phase three-wire model?为什么三相三线制模型里必须区分 $u_{xG}$ 和 $u_{xn}$？

Q3

How does common-mode voltage appear in the inverter but disappear from balanced line-voltage control?共模电压如何出现在逆变器里，却从对称线电压控制中消失？

Q4

Why does a PWM update delay reduce current-loop phase margin?为什么 PWM 更新延迟会降低电流环相位裕度？

Q5

Why is dead-time voltage error current-direction dependent?为什么死区电压误差依赖电流方向？

Q6

Which model would you choose to debug current ripple, low-speed distortion, and current-loop bandwidth?调试电流纹波、低速畸变、电流环带宽时，你会分别选择哪一级模型？